Field of the Invention
The invention relates to a system for testing fast integrated digital circuits, in particular semiconductor modules, e.g. SDRAMs (Synchronous Dynamic Access Memories), in which test signals, such as test data, test control signals, test address signals, and test clock signals are predetermined by a testing device and are supplied to the module to be tested, and the resulting signals that are produced the module undergoing testing and that are dependent upon the test signals are evaluated.
Using existing test systems alone, highly integrated fast digital circuits, such as semiconductor memory modules, that are distinguished by high data rates and clock frequencies cannot be tested economically with the necessary chronological precision and the parallelism required for high-volume production.
In particular, for SDRAMs of generations 64 M to 1 G, having clock frequencies  greater than 150 MHz, there are currently no test systems having sufficient test precision that include the parallelism necessary for an economical testing, i.e., with which a plurality of memory modules can be tested in parallel. The current testing of SDRAMs having double data rate (DDR) involves a reduction of parallelism that is unacceptable for production conditions.
Thus, for the testing of DDR-SDRAMs there currently exists no effective test system that enables the required chronological precision and that has sufficient parallelism for mass production.
Published German Patent application DE 199 28 981 A1 teaches a testing system for testing semiconductor memory units that produces test signals, supplies them to semiconductor memory units that are to be tested, and evaluates result signals produced by these. The known test system can test a plurality of semiconductor memory units simultaneously and can execute a logical comparison process with a correct time controlling, even if the phases of internal clock pulses emitted by a multiplicity of semiconductor memory units to be tested simultaneously are irregular.
Published Japanese Patent application JP 05-264,667 A specifies a testing circuit integrated in an LSI (Large-Scale Integration) semiconductor circuit that obtains a slow clock signal and produces from it a high-speed clock signal, using a frequency multiplier. In addition, test data supplied slowly through the testing circuit are converted into rapid test data by means of parallel-serial converters and multiplexers, which data are supplied, as rapid test data, to a circuit part of the LSI circuit that operates with a high-frequency clock signal.
It is accordingly an object of the invention to provide a testing system that is suitable for testing fast integrated digital circuits, in particular semiconductor memory modules with high data throughput, such as for example SDRAMs, that includes the required chronological precision and at the same time offers the possibility of testing a larger number of digital circuit modules simultaneously, i.e. in parallel. Moreover, it is an object of the invention to provide a semiconductor circuit module (BOST module) that can be used for such a test system.
With the foregoing and other objects in view there is provided, in accordance with the invention a system for testing a semiconductor module, that includes a semiconductor module to be tested that produces signals and that receives a clock signal having a clock frequency; and a testing device for producing relatively slower test signals including background data signals, control signals, address signals, and a clock signal having a frequency. The testing device is also for evaluating the signals produced by the module to be tested. The module to be tested and the testing device define a signal path therebetween. The system also includes an additional semiconductor circuit module inserted into the signal path between the testing device and the module to be tested.
The additional semiconductor circuit module includes: a control unit that is connected to and controlled by the testing device; and an n:1 multiplexer connected to the testing device. The multiplexer is for, during test operation, converting the relatively slower background data signals, control signals, and address signals from the testing device into relatively faster internal signals for controlling background data signals, control signals including write/read signals, and a sequence of address signals that are supplied to the module to be tested. The additional semiconductor circuit module includes a register unit that is connected to the control unit and to the testing device. The register unit is programmable by the testing device. The register unit is configured for controlling the background data signals, the control signals including the write/read signals, and the sequence of the address signals that are supplied to the module to be tested. The additional semiconductor circuit module includes an address counter for producing the sequence of the address signals that are supplied to the module to be tested. The address counter is connected to the testing device, to the programmable register unit, and to the multiplexer. The additional semiconductor circuit module includes a data path connected to the testing device and to the multiplexer for supplying the background data to the module to be tested. The additional semiconductor circuit module includes an internal clock system including a frequency multiplier for multiplying the frequency of the clock signal from the testing device to obtain the clock frequency of the clock signal for the module to be tested. The additional semiconductor circuit module includes an interface unit connected to the module to be tested, to the address counter, to the programmable register unit, to the multiplexer, to the data path, and to the testing device in order to produce high precision output signals that are synchronized by the internal clock system and to achieve precise evaluation times of the signals produced by the module to be tested.
In accordance with an added feature of the invention, the module to be tested is a SDRAM module, and the additional semiconductor module is switchable between a single data rate and a double data rate in dependence upon contents of the register unit.
In other words, the inventive test system is defined by the following measures: An additional semiconductor circuit module (BOST module) is inserted into the signal path between the conventional, relatively slow testing device and the module (Device Under Test DUT) that is to be tested. BOST is an abbreviation that stands for xe2x80x9cBuild Outside Self Test.xe2x80x9d The BOST module has the following functions:
A previously standard, economical testing device controls one or more BOST modules with the relatively slow clock frequencies associated with the testing device.
The BOST module operates the module DUT to be tested with a multiple of the clock frequency of the testing device. The signal sequence, in particular commands, addresses, and data background with which the digital circuit module is tested, is determined both by signals of the testing device and also by contents, programmed before the test, of a register in the BOST module.
With the contents stored in this register, the BOST module can be switched between single-data-rate mode (SDR) and double-data-rate mode (DDR) during the test of an SDRAM.
The BOST module supplies, even at the maximum output frequency, output signals whose edges have a very high degree of chronological precision.
Through variation of the phase position of the output signals, testing of critical setup/hold times is enabled in a manner that is separate for different pin groups (clock, data, addresses). The same holds for the input signals of the BOST module for testing of the access times. The adjustable chronological resolution is a fraction of the clock frequency of the module that is to be tested.
The voltage level of the signals output by the BOST module to the module to be tested or DUT are predetermined by an external voltage level, in particular by the testing device. The same holds for the input signals for testing the signal level of the signals driven by the module to be tested.
The signal runtime between the BOST module and the digital circuit module DUT to be tested is taken into account through feeding the clock signal emitted by the BOST module to the digital circuit module back to the BOST module. In this way, the exact time of evaluation of the data driven by the digital circuit module DUT can be defined.
The BOST module has two operating states:
(a) Before each test of the digital circuit module, the registers of the BOST module for the sequence controlling of the subsequent test are loaded by the testing device;
(b) During the test, the sequence of the output signals to the tested digital circuit module DUT is controlled both via the contents loaded into the register unit and also via the signal values supplied by the testing device.
When, given a parallel test, as is preferred, a BOST module is spatially allocated to each digital circuit module of the same type, a parallel test of, for example, 16 digital circuit modules can be carried out with 16 BOST modules connected between a standard testing device and these digital circuit modules. The BOST modules for a module to be tested at the wafer level are thereby integrated into the probe card. If digital circuit modules are to be tested at the component level, a BOST module is arranged directly underneath the base of the module to be tested.
Using the inventive test system, through the use of the BOST modules, the previously standard, relatively slow testing devices can be further used for testing memory modules, for example SDRAMs, that have high clock frequencies and that also operate in double data rate mode. It is thereby decisive that the high degree of flexibility that standard testing devices offer with regard to programming and the selection of test conditions can be further used, thus ensuring the required test level for the testing of the newest SDRAMs.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a system for testing fast integrated digital circuits, in particular semiconductor memory modules, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.